1. Field of the Invention
The present invention is directed to single phase AC to DC converters with power factor correction (so that the power factor of the input current is at a power factor in excess of that of an otherwise comparable low-power-factor converter design), used, for example, in switching mode power supplies employed with discharge lamps (electronic ballast).
2. Description of the Prior Art
The demand for and development of power factor correction (PFC) circuits has been fueled by a concern over the massive use of electronic power converters, such as, for example, AC-DC-DC and AC-DC-AC power converters employed in electronics ballasts, and the resulting potential for electrical contamination of AC power lines. Because of cost considerations, it is usually desirable to employ a simple PFC circuit and increase the efficiency of the whole system.
PFC circuits are classified into two groups. A first group is defined as active PFC circuits. A second group is defined as passive PFC circuits. Boost-type active PFC circuits are popular due to the efficiency of such a PFC circuit. However, the efficiency of active PFC circuits is still lower than the efficiency of passive PFC circuits, due to, for example, active power switching circuits associated with the active PFC circuits. Further, the control of an active PFC circuit is complex (as compared to passive PFC circuits), resulting in increased manufacturing costs and reduced reliability of the circuit. Since passive PFC circuits do not employ active control circuitry, the manufacturing cost is low and the operating efficiency of the circuit is high (in comparison with active PFC circuits). However, passive PFC circuits exhibit higher levels of total harmonic distortion (THD) of the input current, as compared to active PFC circuits, and the power factor (PF) of passive PFC circuits is not as high as with active PFC circuits.
With respect to passive PFC circuits, valley-fill circuits provide better performance than other passive type PFC circuits, while being low in manufacturing cost. However, such circuits have their own unique problems. A conventional valley-fill circuit typically comprises two electrolytic capacitors C1 and C2, and three rectifying diodes D1, D2 and D3, as shown in FIG. 1.
Around the line peak, capacitors C1 and C2 are charged in series through diode D3 to half of the peak power line voltage. As long as the power line voltage remains above the voltage of each capacitor, the power line directly supplies power to the load. When the power line voltage falls below the voltage of each capacitor (e.g., the voltage falls to a valley voltage), bridge rectifier BR is back-biased, and diodes D1 and D2 become conductive, resulting in capacitors C1 and C2 feeding the load in parallel. Thus, the voltage supplied to the load follows the rectified power line voltage for about 120 degrees of the electrical waveform around the peak and follows the capacitors' voltage for about 60 degrees near the zero line crossing points.
A pulsating line current charges the capacitors near the peak power line voltage, resulting in a deteriorated PF (of about 0.95) and a high THD (e.g., about 40%), as shown in FIG. 2A. The output of the valley fill circuit exhibits a large ripple from the half of the power line peak voltage to the power line peak voltage, with the ripple frequency being equal to twice the line frequency, as shown in FIG. 2B.
In the valley fill circuit, the power line directly feeds energy (e.g., electrical energy) to the load through the rectifier diodes for approximately 120 degrees around the peak voltage. As noted above, capacitors C1 and C2 feed energy to the load through diodes D1 and D2 for approximately 60 degrees near (proximate) the zero line crossing points. Most of the input energy is directly fed to the load, with a small portion of the input energy being first fed to capacitors C1 and C2, and then fed to the load through capacitors C1 and C2. As a result, such a circuit offers a relatively high operating efficiency.
A great deal of time and effort has been spent in attempts to improve the PFC performance of valley-fill circuits. This work has been directed to shaping the input current during the approximate 60 degree dead time near the zero line crossing points, and to limiting the pulsating line current that charges the capacitors near the peak line voltage.
A paper entitled "A Unity Power Factor Electronic Ballast for Fluorescent Lamp Having Improved Valley Fill and Valley Boost Converter" from Conference Record PESC'97, describes the use of an active boost circuit to shape the input current during the approximate 60 degree dead time near the zero line crossing points, as shown in FIG. 3. Because a boost switch still suffers the peak input voltage and the switch only works during the 60 degree dead time, as shown in FIG. 4, a complex control method is required. In addition, the complexity of the circuit increases the total manufacturing cost.
U.S. Pat. No. 5,764,496 illustrated in FIG. 5, discloses the use of a high frequency output voltage or current of an inverter to drive a charge pump circuit Z. As shown in FIG. 5, the charge pump circuit shapes the input current during the approximate 60 degree dead time and charges two electrolytic capacitors C1 and C2. The two electrolytic capacitors C1 and C2 are not directly charged from the power line, so as to avoid the pulsating line current. However, because the charge pump is driven by the inverter and the charge pump works full time, the active switches are exposed to extra current and/or voltage stresses.
Japanese Patent HEI 8-205520, illustrated in FIG. 6, describes the load current of a PFC converter as being discontinuous, and discloses that the insertion of a suitable inductor L1 in the input power line avoids (prevents) pulsating of the power line current. Because an instantaneous line voltage is higher than the voltage of each DC bulk capacitor C1 and C2, while being less than the sum of the voltages of the two capacitors, the inserted inductor provides a boost function to boost the sum of the voltage of the two capacitors. However, this disclosure fails to solve the above-described problem that exists at the input current during the approximate 60 degree dead time near the zero line crossing points.